1. Field of the Invention
This invention relates to tools for analyzing circuits, and more particularly, to modeling behavior of an electrical circuit.
2. Related Art
Modeling of circuits is an important part of the process of bringing an integrated circuit from a concept to an actual product. Modeling provides a much faster and cheaper way to verify that a design actually does what is intended. This includes all aspects of the operation of the circuit, not just that the circuit performs the intended analog or logic function. Power consumption, for example, is becoming one of the most important factors in the design of VLSI systems in recent years due to increased integration level and higher clock frequency. Integrated circuits with high power consumption levels have stringent requirements on heat removal and management of di/dt noise. High current consumption also shortens battery life of portable electronics. Detailed and accurate power analysis on a clock cycle by clock cycle basis is therefore imperative not only to quantify the requirements of heat removal and di/dt noise management, but also to provide a blueprint for opportunities of reducing power consumption and mitigating di/dt noise in a circuit design. Thus it is important to be effective in modeling power consumption.
Power consumption can be estimated at high-level, gate-level, and transistor-level with a trade-off between estimation accuracy and simulation speed. Power estimation on a clock cycle by clock cycle basis is normally only feasible by using the gate-level or transistor-level approach. The transistor-level method provides better accuracy, but its requirement of a relatively long simulation time prevents it from being used to study a large number of test vector sequences in a large and complex design, e.g., a microprocessor. In the gate-level method, switching activities beyond gates are captured by behavioral simulation. This provides much better simulation speed. Cycle-by-cycle power consumption resulting from the charging and discharging of capacitors of interconnects and gates' inputs can be easily evaluated. On the other hand, the power consumption internal to gates needs to be pre-characterized under different steady state and switching conditions. Power estimation accuracy of the gate-level method depends on how well the power consumption of gates is characterized.
Accordingly there is a need for a tool for improving estimation accuracy and speed of power consumption of an integrated circuit.